The Generated Code

There are three Verilog modules: the LFSR counter, a decrementing counter used to compare the count to and test code that displays the results or discrepancies. The LFSR counter module is implemented as a shift register with exclusive-or tree feedback. The shift register uses data steering logic for holding the count by recirculating the shift register data and presetting to the starting seed value. End of count  occurs when the shift register outputs are all set to one. End of count or terminal count is detected with and/nand logic or with an auxiliary counter.

The parameters and module name can be redefined in the “Labels” window. They must be valid Verilog identifiers, that is, start with A-Z, a-z, _ and follow with A-Z, a-z, _ , $, or 0-9. The identifiers will be checked before generating the text. In the “Parameter” window,  the count value is input, optional parameters are enabled or disabled, signal polarity is selected for high or low activation, and the type of counter selected.

Count

The count is a positive decimal integer from 2 to 2,147,483,648. The count is the number of active clock edges from  preset deasserting to  terminal count asserting (end of count). 

Clock Enable Input - Optional Parameter

Clock enable input holds the counter from counting when asserted. If this parameter is disabled, no clock enable circuitry is generated and it is not defined in the module parameter list. The clock enable input is a synchronous signal which must satisfy setup time before the active clock edge. The shift register data is recirculated while clock enable is asserted.

Terminal Count Output - Optional Parameter

The terminal count indicates the counter’s end of count state. The counter asserts this when all bits in the shift register reach all ones. Terminal count is asserted a propagation delay behind the active clock edge and remains asserted for one clock cycle. If this parameter is disabled, terminal count is generated internally; however, it is not brought out in the module parameter list. 

Shift Register Output - Optional Parameter

The output stages of the shift register can be made available in the module parameter definition for FIFO address generators and other special counting purposes.  The shift registers are stable, a propagation delay after active clock edge. During preset, the shift register value is the initial seed. During clock enable, the shift register remains unchanged. In a one shot counter after terminal count, the shift register will left shift zeros and then recirculate  zeros until preset.  

Retriggerable - Counter Type

The counter can be retriggerable or one shot. The retriggerable counter presets itself on every terminal count (in addition to preset). One application of this is as a high speed prescaler. Terminal count need not be brought out for this to operate. 

One Shot - Counter Type 

The one shot counter ceases counting after terminal count until another preset is asserted. This is done by forcing the initial shift register stage input to zero instead of feeding back the exclusive or tree. In LFSR counters, zero state will always recirculate zeros. A set reset flip flop is set by the preset signal and cleared by terminal count. 

Clock Edge - Signal Polarity

The counter can be configured to count on a positive or negative transition. All input and output transitions will reference from the selected edge. The counter is implemented with a case/always, similar to a common Verilog state machine inference.
 
Clock Enable - Signal Polarity

The clock enable, if enabled  can be asserted when active high or active low. The clock enable holds the counter from counting when it is asserted and counts when deasserted. The clock enable input is a synchronous signal which must satisfy setup time before the active clock edge. The shift register data is recirculated while clock enable is asserted.

Terminal Count - Signal Polarity

The terminal count, if enabled will be asserted as active high or active low. When  terminal count is asserted, it  indicates the counter’s end of  state. Terminal count is asserted a propagation delay behind the active clock edge and remains asserted for one clock cycle.

Preset - Signal Polarity

The preset input can be asserted when active high or active low. The preset signal is  a synchronous initialization of the counter. When asserted the counter is preset to it’s seed value. 

AND/NAND Detect - Terminal Count Logic

The terminal count logic can be implemented one of two ways: and/nand detect or auxiliary ‘1’ counter. The and/nand detect is suitable for small counters with few stages. An and or nand gate (depending on terminal count polarity) is used to detect all ones from the shift register output. 

Auxiliary ‘1’ Counter - Terminal Count Logic

The auxiliary ‘1’ counter counts the number of ones that have been shifted into the main shift register.  When the last one is shifted in, the auxiliary ‘1’ counter asserts it’s terminal count as the main counter’s terminal count. The auxiliary counter is another small LFSR counter whose count is the number of stages in the main counter. A zero shifted in will preset the counter. The auxiliary counter operation is in tandem with the main shift register. All operations that can be done on the main counter are done with the auxiliary counter. The auxiliary ‘1’ counter should be used when for large counts where and/nand gates are to large for fast response.